An integrated circuit (IC), such as an application specific integrated circuit (ASIC) or the like, are designed using design for testability (DFT) techniques. DFT techniques add testability features to a circuit design, such as scan chains. A scan chain is formed by a number of flip-flops (“flops”) connected sequentially in a chain. The input of the first flop is connected to an input pin (a “scan-in”) and the output of the last flop is connected to an output pin (a “scan-out”). Scan chains are inserted into designs to shift in test input data and shift out test result data.
IC manufacturers perform scan testing for various reasons, including to test stuck-at faults, to test the paths for delay (e.g., to determine if a path is operating at a functional frequency), and the like. Such scan testing is typically performed using automated test equipment (ATE) during manufacture. An IC can make use of scan compression to reduce the amount of data needed to test the IC, which frees up resources of the ATE and can reduce testing costs.
An IC can also be designed to perform self-testing using a logic built-in-self test (LBIST) feature. LBIST can test circuitry in the field and can test internal circuits that have no direct connections to external pins. LBIST can also provide test input to and receive test output from scan chains. An IC can perform LBIST upon being powered on.
Power-on LBIST typically exhibits run-time limitations so that the power-on time for a device meets specifications. To meet run-time limitations, LBIST can make use of smaller scan chains (e.g., scan chains having less flops). Conversely, manufacturing scan tests make use of larger scan chains (e.g., scan chains having more flops). For manufacturing scan tests, reducing scan chain length increases compression ratio. Increasing the compression ratio beyond a certain point affects test coverage. Thus, there is a conflict in terms of scan chain lengths in ICs that include both LBIST and manufacturing scan compression/decompression features.